A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of device and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array, is made small by omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit-line and a word-line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source, drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell 8 is depicted in FIG. 1a. As shown, memory cell 8 is viewed in a cross-section through the bit-line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and within which a source 13a and a drain 13b have been formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polysilicon.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13a. When programmed, floating gate 16 will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate 16 does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13a.
FIG. 1b depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective II, as referenced in FIG. 1a). In FIG. 1b, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1b shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a portion of a floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a-b. Interpoly dielectric layer 24 has been conformally deposited over the exposed portions of floating gates 16a-c and field oxide regions 14a-b. Interpoly dielectric layer 24 isolates floating gates 16a-c from the next conformal layer which is typically a polysilicon layer that is subsequently patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
Control gate 26, which is one of a plurality of control gate structures, is formed over interpoly dielectric layer 24 by depositing a layer of polysilicon on interpoly dielectric layer 24. Next, silicide layer 28 is formed on interpoly dielectric 24. Additional layers of material may also be deposited over silicide layer 28, such as, cap layer 30, and one or more dielectric layers 32 and 33, for example. Cap layer 30 is typically a layer of polysilicon that reduces stress in the silicide layer 28. Dielectric layers 32 and 33 typically include silicon dioxide, silicon oxynitride and/or silicon nitride, which are formed using conventional deposition techniques. The resulting layers are then selectively patterned to form control gate structures.
The shrinking of semiconductor devices, and in particular the features depicted in the memory cells of FIGS. 1a-b, places a burden on the fabrication processes, because the shape, size and location of floating and control gate structures are of fundamental importance to the memory cell. In certain reduced size semiconductor devices, such as, for example, the memory cells in FIGS. 1a-b, selective etching processes can cause a silicide residue to form during the etching away of selected portions of silicide layer 28. This silicide residue hinders the subsequent etching of the underlying layer, for example, an underlying layer of polysilicon. Thus, there is a need for methods for controlling the formation processes, such as a control gate etching process, to effectively remove silicide residue during fabrication.